Assisted in design and verification of memory compilers
Optimized design for PPA and functionality
Performed logic equivalence checks
Performed margin checks to ensure circuit functionality different Process, Voltage and Temperature
Performed characterization using XPS, SPECTRE and HSPICE to provide timing and power
information described inside Liberty views which is used by SOC designers
Performed IR drop and EM analysis to ensure design can work for 10 years at elevated temperature
Defined Array Blocks and Pitch Cells, Verified proper signal widths and metal layers
Understood the impact of array architecture decisions on overall power, speed, and die size
Chose appropriate transistor sizes and types for pitch cells for margin and performance
Oversaw and Manage the Layout Process, Managed floor-planning process, including placement and
routing optimization